1. Field of the Invention
This invention relates to an output buffer circuit, and more particularly, to reducing power consumption of an output buffer circuit.
2. Description of the Background Art
Outputs of various circuits such as logic circuits and memory circuits are provided with output buffer circuits in order to increase load driving capability. FIG. 7 is a circuit diagram showing one example of a configuration of a conventional buffer circuit.
In FIG. 7, an output buffer circuit 10a has an input terminal 13 receiving signals from various circuits and an output terminal 14 for producing output signals. An external load 20 is connected to output terminal 14. Output buffer circuit 10a comprises a pull-up transistor formed of a P channel MOS transistor and a pull-down transistor formed of an N channel MOS transistor. Pull-up transistor 11 is connected between a power supply terminal 15 and output terminal 14. A pull-down transistor 12 is connected between a ground terminal and output terminal 14. The gates of pull-up transistor 11 and pull-down transistor 12 are connected to an input terminal 13. External load 20 comprises an external load capacitance 21 and an external load resistance 22.
When a signal applied to input terminal 13 is at "L" (low logic level), pull-up transistor 11 is turned on and pull-down transistor 12 is turned off. As a result, an output signal derived from output terminal 14 attains "H" (high logic level), and external load capacitance 21 is charged. When a signal applied to input terminal 13 is at "H", pull-up transistor 11 is turned off and pull-down transistor 12 is turned on. As a result, an output signal derived from output terminal 14 falls down to "L" and external load capacitance 21 is discharged.
Pull-up transistor 11 and pull-down transistor 12 are normally about ten times the size of the smallest transistor in a semiconductor integrated circuit, so that the load driving capability increases.
As mentioned above, in a conventional output buffer circuit, charging current and discharging current for an external load capacitance 21 all flow through pull-up transistor 11 or pull-down transistor 12, so that a problem exists that power consumption increases due to heat loss of transistor resistance.